1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a metal interconnect line using a CMP (Chemical Mechanical Polishing) process. The invention relates also to a semiconductor device manufactured by the above-mentioned method.
2. Description of the Background Art
A semiconductor integrated circuit comprises a multiplicity of semiconductor devices formed on a main surface of a semiconductor substrate in a device formation region. The semiconductor devices are electrically isolated from each other by an isolating insulation film such as STI (Shallow Trench Isolation) formed in the main surface of the semiconductor substrate in an isolation region. To accomplish the function of the semiconductor integrated circuit, the semiconductor devices are electrically connected to each other by an electrical conductor such as an interconnect line.
The electrical conductor commonly used includes metal or heavily doped polysilicon. The material of the metal interconnect line is aluminum, copper, tungsten, molybdenum, or the like. The material of a gate electrode which is an interconnect line formed on the main surface of the semiconductor substrate is aluminum, polysilicon, a two-layer structure comprised of polysilicon and metal silicide, tungsten, molybdenum, or the like. Metal used for the metal silicide is tungsten, cobalt, nickel, titanium, zirconium, platinum, or the like.
With recently decreasing size of semiconductor integrated circuits, the operating speed of semiconductor devices has been dominated by the performance of multi-level interconnect lines, rather than the performance of MOS transistors themselves, since a 0.18-xcexcm line width generation. In recent years, attention has accordingly been focused on a copper interconnect line having a resistivity lower than that of an aluminum interconnect line which has been a conventionally dominant metal interconnect line. At 20xc2x0 C., copper has a resistivity of 1.70 xcexcxcexa9xc2x7cm, whereas aluminum has a resistivity of 2.74 xcexcxcexa9xc2x7cm.
Since aluminum is anisotropically etchable, a conventional process for forming an aluminum interconnect line comprises depositing an aluminum film on an entire wafer surface, forming a photoresist on the aluminum film by a photolithographic process, and anisotropically etching the aluminum film by using the photoresist as a mask. On the other hand, a technique for anisotropically etching copper has not yet been currently established. To form a copper interconnect line, a process known as a damascene process is employed which comprises anisotropically etching an interlayer insulation film to form a trench, forming a copper film on an entire surface of the interlayer insulation film so as to fill the trench by an electroplating or CVD process, and polishing away an excess part of the copper film which is formed on the interlayer insulation film by a CMP process to form a copper interconnect line in the trench.
FIG. 15 is a cross-sectional view of a background art semiconductor device comprising copper interconnect lines formed using the damascene process. A channel stopper 102 in the form of a layer is formed in a p-type semiconductor substrate 101. An STI 103 is formed in a main surface of the semiconductor substrate 1 in an isolation region. An nMOS transistor is manufactured in the semiconductor substrate 101 in a device formation region. The nMOS transistor comprises: a gate structure 106 selectively formed on the main surface of the semiconductor substrate 101 and having a multi-layer structure including a gate insulation film 104 and a gate electrode 105 formed on the gate insulation film 104; an insulation film 107 and a sidewall 108 which cover upper and side surfaces of the gate structure 106; and source/drain regions selectively formed in the main surface of the semiconductor substrate 101 and including nxe2x88x92 type doped regions 109 of a relatively low concentration and n+ type doped regions 110 of a relatively high concentration. A metal silicide 111 is formed on and in an upper surface of the doped regions 110.
An FSG (fluorosilicate glass) film 112 is formed on entire surfaces of the STI 103 and nMOS transistor, and a silicon nitride (Si3N4) film 113 is formed on an entire surface of the FSG film 112. Contact holes 114 extending from an upper surface of the silicon nitride film 113 to an upper surface of the metal silicide 111 are selectively formed in the FSG film 112 and the silicon nitride film 113. A barrier metal 115 is formed on a side surface of each of the contact holes 114, and a tungsten plug 116 is formed to fill each of the contact holes 114 with the barrier metal 115 formed on the side surface thereof.
An FSG film 117 is formed on an entire surface of the silicon nitride film 113, and a silicon oxynitride (SiON) film 118 is formed on an entire surface of the FSG film 117. Contact holes 119 extending from an upper surface of the silicon oxynitride film 118 to an upper surface of the tungsten plugs 116 are selectively formed in the FSG film 117 and the silicon oxynitride film 118. A barrier metal 120 is formed on side and bottom surfaces of each of the contact holes 119, and a copper interconnect line 121 is formed to fill each of the contact holes 119 with the barrier metal 120 formed on the side and bottom surfaces thereof. A silicon nitride film 122 is formed on an entire surface of the silicon oxynitride film 118.
A TEOS (tetraethylorthosilicate) film 123 is formed on an entire surface of the silicon nitride film 122, and an FSG film 124 is formed on an entire surface of the TEOS film 123. A silicon oxynitride film 125 is formed on an entire surface of the FSG film 124. A contact hole 126 extending from an upper surface of the silicon oxynitride film 125 to an upper surface of one of the copper interconnect lines 121 is selectively formed in the TEOS film 123, the FSG film 124 and the silicon oxynitride film 125. A barrier metal 127 is formed on side and bottom surfaces of the contact hole 126, and a copper interconnect line 128 is formed to fill the contact hole 126 with the barrier metal 127 formed on the side and bottom surfaces thereof. More specifically, part of the copper interconnect line 128 which lies below an upper surface of the TEOS film 123 functions as a copper plug for establishing an electric connection between the lower-level copper interconnect line 121 and part of the upper-level copper interconnect line 128 which lies above the upper surface of the TEOS film 123.
A trench 129 extending from the upper surface of the silicon oxynitride film 125 to a bottom surface of the FSG film 124 is selectively formed in the FSG film 124 and the silicon oxynitride film 125. A barrier metal 130 is formed on side and bottom surfaces of the trench 129, and a copper interconnect line 131 is formed to fill the trench 129 with the barrier metal 130 formed on the side and bottom surfaces thereof. A silicon nitride film 132 is formed on an entire surface of the silicon oxynitride film 125. The components ranging from a bottom surface of the TEOS film 123 to an upper surface of the silicon nitride film 132 serve as a single unit 133 of an interconnect layer. A protective film 134 is formed on an entire surface of the silicon nitride film 132.
The barrier metals 120, 127, 130 have the function of preventing copper atoms constituting the copper interconnect lines 121, 128, 131 from diffusing or drifting into the FSG films 117, 124 to degrade an insulating property.
A process for forming only the copper interconnect line 131 and the part of the copper interconnect line 128 which lies above the upper surface of the TEOS film 123 in the single interconnect layer unit 133 is known as a single damascene process. On the other hand, a process for forming the part of the copper interconnect line 128 which lies above the upper surface of the TEOS film 123 and the part of the copper interconnect line 128 which is below the upper surface of the TEOS film 123 (or the copper plug) in the same step is known as a dual damascene process. A method of forming the single interconnect layer unit by the single damascene process will be described below.
FIGS. 16 through 21 are cross-sectional views showing a method of manufacturing the background art semiconductor device in a step-by-step manner. First, the FSG film 124 is formed on the entire surface of the TEOS film 123 by a CVD or PVD process, and the silicon oxynitride film 125 is formed on the entire surface of the FSG film 124 by a CVD or PVD process (FIG. 16). The relative dielectric constants of these respective insulation films are as follows: the TEOS film 123 about 3.8-4.2, the FSG film 124 about 3.5-3.7, and the silicon oxynitride film 125 about 4.3-7.0. The relative dielectric constant of the silicon oxynitride film 125 increases with increasing nitrogen content. As a pitch between the interconnect lines decreases, a wiring capacitance between two adjacent interconnect lines in the same interconnect layer increases. Thus, the use of an insulation film having a lower relative dielectric constant (the FSG film 124 in this case) as the insulation film provided between adjacent interconnect lines reduces the wiring capacitance.
The silicon oxynitride film 125 is formed on the FSG film 124 to prevent an upper part of the FSG film 124 from being polished away during copper polishing in a subsequent CMP process. The decrease in thickness of the FSG film 124 due to the removal of the upper part thereof by polishing increases a wiring capacitance between different interconnect layers. However, this is prevented by forming the silicon oxynitride film 125 on the FSG film 124. In other words, the silicon oxynitride film 125 functions as a film for preventing polishing of the FSG film 124 during the copper polishing by the CMP process.
Next, a photoresist 136 having a predetermined opening pattern is formed on the silicon oxynitride film 125 by a photolithographic process. Using the photoresist 136 as a mask, an anisotropic dry etching process which exhibits a higher etch rate in a depth direction is performed to etch the silicon oxynitride film 125 and the FSG film 124 in the order named, exposing the upper surface of the TEOS film 123. As a result, the trenches 129 are formed each of which includes the side surface constructed of the silicon oxynitride film 125 and the FSG film 124 and the bottom surface constructed of the TEOS film 123, and has a depth 137 equal to the sum of the thicknesses of the silicon oxynitride film 125 and the FSG film 124 (FIG. 17). Under conditions of a higher etch selectivity between the FSG film and the TEOS film, etching can be stopped as soon as the upper surface of the TEOS film 123 is exposed. For etching under conditions of a lower etch selectivity therebetween, an etch time may be controlled in accordance with the sum of the thicknesses of the silicon oxynitride film 125 and the FSG film 124 to adjust the depth 137 of the trenches 129.
The photoresist 136 is removed, and then a barrier metal 138 is formed on the side and bottom surfaces of the trenches 129 and on the upper surface of the silicon oxynitride film 125 by a sputtering process or the like (FIG. 18). The material of the barrier metal 138 is tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or the like.
A copper film 139 is formed on an entire surface of a resultant structure by an electroplating or CVD process. The copper film 139 fills the trenches 129 and is has an upper surface which is above the upper surface of the silicon oxynitride film 125 (FIG. 19).
Next, the copper film 139 and the barrier metal 138 are polished away in the order named by a CMP process until the upper surface of the silicon oxynitride film 125 is exposed. Parts of the copper film 139 which are left unpolished become the copper interconnect lines 131 filling the trenches 129. Parts of the barrier metal 138 which are left unpolished become the barrier metals 130 (FIG. 20).
The CMP process for copper comprises the following three basic steps:
(1) chemically producing a protective film for preventing copper etching on a surface of the copper film;
(2) physically removing only a raised part (on the atomic level) of the protective film by polishing using a polishing cloth; and
(3) etching away, using a polishing agent, a raised part of copper which is exposed by the removal of the protective film.
As an example, the CMP process for copper using a glycine (NH2CH2COOH) base polishing agent is described below. First, a copper surface is oxidized by a hydrogen peroxide solution to provide a CuO film serving as an etch protection film. Only a raised part of the CuO film is physically removed by polishing using a polishing cloth, and thus exposed copper in the intermediate oxidation state (Cu(H2O)42+ or Cu2O) reacts with glycine. The reaction of Cu(H2O)42+ and glycine is expressed as:
Cu(H2O)42++2NH2CH2COOHxe2x86x92Cu(NH2CH2COOH)2+4H2O+2H+xe2x80x83xe2x80x83(1)
As given by the reaction formula (1), the reaction of copper in the intermediate oxidation state and glycine forms a copper-glycine complex. The copper-glycine complex is dissolved in water which is a by-product of the reaction. The silicon oxynitride film 125 serving as an underlying layer of the barrier metal 138 is removed little by an etchant used in the CMP process for the copper film 139.
Then, the silicon nitride film 132 is formed on an entire surface of a resultant structure to cover the copper interconnect lines 131 by a CVD process or the like (FIG. 21). The reason why the silicon nitride film 132 is formed is as follows: Decreasing the wiring resistance requires the prevention of surface oxidation of the copper interconnect lines 131 since CuO which is an oxide of copper is insulative. CuO is formed not only when copper is exposed to atmosphere but also when the copper surface is cleaned by an oxidizing cleaning fluid or when copper is polished in a CMP process. Therefore, it is desirable to reduce the thickness of the CuO film serving as the etch protection film, for example, in the CMP process for copper.
Unfortunately, such a background art method of manufacturing a semiconductor device presents problems to be described below.
FIG. 22 is a schematic view for illustrating the wiring capacitance between two adjacent interconnect lines in the same interconnect layer in corresponding relation to the structure shown in FIG. 21. The thickness of the silicon oxynitride film 125 is designated by t1, and the relative dielectric constant thereof is designated by ∈1. The thickness of the FSG film 124 is designated by t2, and the relative dielectric constant thereof is designated by ∈2. A spacing between the left-hand and right-hand copper interconnect lines 131 shown in FIG. 22 is designated by d. The barrier metals 130 are regarded as part of the copper interconnect lines 131. The wiring capacitance between the two copper interconnect lines 131 shown in FIG. 22 is designated by C1 in a portion lying on opposite sides of the silicon oxynitride film 125 and by C2 in a portion lying on opposite sides of the FSG film 124. The total wiring capacitance C0 per unit length is expressed as:
C0=C1+C2=∈1∈0t1/d+∈2∈0t2/dxe2x80x83xe2x80x83(2)
where ∈0 is a dielectric constant in a vacuum. The wiring capacitances C0, C1, C2 will be determined from Equation (2), for example, when ∈1=6.0, ∈2=3.7 and d=0.2. FIG. 23 is a graph showing plots of the wiring capacitances C0, C1, C2 versus the thickness t1 taking on various values when t1+t2 is fixed at 400 nm. The graph of FIG. 23 shows that the smaller the thickness t1 of the silicon oxynitride film 125, the lower the wiring capacitance C0. FIG. 24 is a graph showing plots of the wiring capacitances C0, C1, C2 versus the relative dielectric constant ∈1 assumed to take on various values when t1=50 nm and t2=350 nm. The graph of FIG. 24 shows that the smaller the relative dielectric constant ∈1 of the silicon oxynitride film 125, the lower the wiring capacitance C0.
From the above, it will be found desirable to use an insulation film made of a material resistant to copper polishing by the CMP process and having a low relative dielectric constant as the film for preventing polishing of the FSG film and yet to form the insulation film thinly on the FSG film in order to reduce the wiring capacitance between adjacent interconnect lines.
However, no insulation film which is as resistant to copper polishing as the silicon oxynitride film and which has a lower relative dielectric constant than does the silicon oxynitride film is known at the present time. Therefore, the silicon oxynitride film is optimum as the film for preventing polishing of the FSG film in the state of the art technology, and other than the technique of reducing the thickness of the silicon oxynitride film finds difficulties in further reducing the wiring capacitance between adjacent interconnect lines.
Second Problem FIG. 25 is a cross-sectional view of a semiconductor device manufactured by a background art semiconductor device manufacturing method and comprising the two levels of copper interconnect lines 121 and 128. The size reduction of the semiconductor device having a multi-level interconnection structure reduces the contact area of the upper-level copper interconnect line 128 (or barrier metal 127) and the lower-level copper interconnect lines 121 to inevitably increase an interface resistance. However, the semiconductor device manufactured by the background art semiconductor device manufacturing method presents such a problem that the interface resistance increases by an amount greater than the amount of increase resulting from the reduction in contact area.
Known causes for such a phenomenon include a foreign material which is produced by the reaction of an etching gas used to etch the silicon nitride film 122 and the copper interconnect lines 121 and is present at a contact interface, and a copper oxide film having a high insulating property (a CuO film 140 shown in FIG. 25) which is present in the upper surface of the copper interconnect lines 121. The CuO film 140 is formed by natural oxidation of the upper surface of the copper interconnect lines 121 between the step of forming the copper interconnect lines 121 and the step of forming the silicon nitride film 122 or is formed when the CuO film used as the etch protection film for the copper interconnect lines 121 in the CMP process is left in the upper surface of the copper interconnect lines 121. The CuO film 140 has a thickness ranging from about tens of nanometers to about hundreds of nanometers. However, the greater the amount of overpolishing of the copper film in the CMP process, the greater the amount of remaining CuO film as the etch protection film and accordingly the thicker the CuO film 140. The thicker the CuO film 140, the higher the interface resistance and the wiring resistance itself because of a smaller cross-sectional area of the copper interconnect lines 121.
This problem is solved by cleaning away the CuO film 140 exposed at the bottom surface of the contact hole before forming the upper-level barrier metal 127. However, the CuO film 140 is not sufficiently cleaned and accordingly is not completely removed in practice because of the small diameter of the contact hole, in particular, in a size-reduced semiconductor device.
A first aspect of the present invention is intended for a method of manufacturing a semiconductor device. According to the present invention, the method comprises the steps of: (a) forming an insulation film on an underlying layer, the insulation film including a noble gas atom containing layer in an upper surface thereof, the noble gas atom containing layer containing a noble gas atom; (b) selectively removing the insulation film until the underlying layer is exposed to form a trench; (c) forming a metal film on a structure resulting from the step (b); and (d) polishing away the metal film until the upper surface of the insulation film is exposed.
Preferably, according to a second aspect of the present invention, in the method of the first aspect, the insulation film is formed by deposition in the step (a); and the noble gas atom containing layer is formed by introducing the noble gas atom into the insulation film during the deposition of the insulation film.
Preferably, according to a third aspect of the present invention, in the method of the first or second aspect, the insulation film contains a fluorine atom. The method further comprises the steps of: (e) releasing from the insulation film the fluorine atom contained in part of the insulation film which is near a side surface thereof exposed by formation of the trench, the step (e) being performed between the steps (b) and (c); and (f) forming a barrier metal on the side surface of the insulation film and an upper surface of the underlying layer which are exposed by the formation of the trench, the step (f) being performed between the steps (e) and (c), wherein the metal film is formed on the barrier metal in the step (c).
Preferably, according to a fourth aspect of the present invention, in the method of the third aspect, the step (e) is performed by heat-treating a structure resulting from the step (b).
A fifth aspect of the present invention is intended for a method of manufacturing a semiconductor device. According to the present invention, the method comprises the steps of: (a) selectively forming a first metal interconnect line in an upper surface of a first insulation film; (b) forming a second insulation film on the first insulation film; (c) selectively trenching an upper surface of the second insulation film to form a trench, thereby exposing an upper surface of the first metal interconnect line; (d) introducing an impurity into the upper surface of the first metal interconnect line; (e) cleaning the upper surface of the first metal interconnect line, the step (e) being subsequent to the step (d); (f) forming a metal film on a structure resulting from the step (e); and (g) polishing away the metal film until the upper surface of the second insulation film is exposed to form a second metal interconnect line.
Preferably, according to a sixth aspect of the present invention, in the method of the fifth aspect, the impurity includes noble gas atoms; and the step (d) is performed by ion-implanting the noble gas atoms at an energy of 5 to 30 keV and at a dose of 1xc3x971013 to 1xc3x971015/cm2.
Preferably, according to a seventh aspect of the present invention, in the method of the fifth aspect, the impurity is introduced also into a side surface of the second insulation film exposed by formation of the trench in the step (d); and the impurity introduced is selected from the group consisting of silicon, oxygen and ozone.
Preferably, according to an eighth aspect of the present invention, in the method of the fifth aspect, the impurity is introduced also into a side surface of the second insulation film exposed by formation of the trench in the step (d); and the impurity introduced is nitrogen.
Preferably, according to a ninth aspect of the present invention, in the method of the eighth aspect, the step (d) is performed by ion-implanting the nitrogen at an energy of 5 to 30 keV and at a dose of 5xc3x971013 to 5xc3x971015/cm2.
A tenth aspect of the present invention is intended for a method of manufacturing a semiconductor device. According to the present invention, the method comprises the steps of: (a) forming an insulation film containing a fluorine atom on an underlying layer; (b) selectively removing the insulation film until the underlying layer is exposed to form a trench; (c) releasing from the insulation film the fluorine atom contained in part of the insulation film which is near a side surface thereof exposed by formation of the trench; (d) forming a barrier metal on the side surface of the insulation film and an upper surface of the underlying layer which are exposed by the formation of the trench, the step (d) being performed after the step (c); (e) forming a metal film on the barrier metal; and (f) polishing away the metal film until the upper surface of the insulation film is exposed.
Preferably, according to an eleventh aspect of the present invention, in the method of the tenth aspect, the step (c) is performed by heat-treating a structure resulting from the step (b).
A twelfth aspect of the present invention is intended for a semiconductor device manufactured by the method of any one of the first to eleventh aspects.
In the method of the first aspect, when the metal film is polished away in the step (d), the surface of the noble gas atom containing layer is covered with noble gas atoms with a certain surface density. This suppresses an etching reaction between the atoms constituting the noble gas atom containing layer and a polishing agent. Therefore, the polishing is easily stopped at the point of time at which the upper surface of the insulation film is exposed.
The method of the second aspect, unlike a process for introducing noble gas atoms by ion implantation, can avoid the occurrence of radiation damage in the insulation film.
In the method of the third aspect, the release of the fluorine atom contained in the insulation film near the side surface thereof prevents the fluorine atom from moving into the barrier metal. Therefore, the removal of the insulation film and the barrier metal from each other is avoided.
In the method of the fourth aspect, the fluorine atom contained in the insulation film is released from the insulation film by a simple heat treatment process. hi the method of the fifth aspect, if an oxide of metal is formed by natural oxidation in the upper surface of the first metal interconnect line, the introduction of the impurity in the step (d) can destroy the oxide of metal. Therefore, the oxide of metal is easily removed when the upper surface of the first metal interconnect line is cleaned in the step (e).
The method of the sixth aspect can effectively destroy the oxide of metal formed in the upper surface of the first metal interconnect line.
The method of the seventh aspect can improve intimate contact between the second metal interconnect line and the second insulation film.
The method of the eighth aspect can improve intimate contact between the second metal interconnect line and the second insulation film. Additionally, the method of the eighth aspect can prevent a metal atom constituting the second metal interconnect line from moving into the second insulation film and prevent an atom contained in the second insulation film from moving into the second metal interconnect line.
The method of the ninth aspect can effectively destroy the oxide of metal formed in the upper surface of the first metal interconnect line.
In the method of the tenth aspect, the release of the fluorine atom contained in the insulation film near the side surface thereof prevents the fluorine atom from moving into the barrier metal. Therefore, the removal of the insulation film and the barrier metal from each other is avoided.
In the method of the eleventh aspect, the fluorine atom contained in the insulation film is released from the insulation film by a simple heat treatment process.
In accordance with the twelfth aspect, the semiconductor device which is short in delay time and high in operating speed is accomplished since a wiring capacitance between adjacent interconnect lines is reduced.
It is therefore an object of the present invention to overcome the first problem by providing a method of manufacturing a semiconductor device which can avoid the use of a silicon oxynitride film having a high relative dielectric constant as a film for preventing polishing of an FSG film while ensuring resistance to polishing of a metal film by a CMP process, thereby to reduce a wiring capacitance between adjacent interconnect lines.
It is another object of the present invention to overcome the second problem by providing a method of manufacturing a semiconductor device having a multi-level interconnection structure which can suitably remove an oxide of metal present in an upper surface of a lower-level interconnect line before the step of forming an upper-level interconnect line, thereby to reduce an interface resistance and a wiring resistance.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.